1. Field of the Invention
The invention relates to binarization processing apparatus and method for converting multi-value data such as image data having a gradation which is used in an image forming apparatus such as display apparatus, printer, or the like into binary data and, more particularly, to binarization processing apparatus and method suitable to binarize a half-tone image.
2. Related Background Art
As an explanation of a conventional binarization processing apparatus for binarizing multi-value data such as a half-tone image, a binarizing process according to an error diffusing method will now be described as an example. According to an error diffusing process, by deciding a color by a threshold value for multi-value data having a gradation indicative of a density and distributing a difference between a density value of the decided color and a density value of an actual pixel as an error to pixels around a target pixel, the binarizing process is performed while preserving the density of the multi-value data.
A display apparatus having a binarization processing apparatus has already been filed to the United States Patent and Trademark Office on Oct. 5, 1994, as application Ser. No. 318,299.
FIG. 1 shows an example of a conventional binarization processing apparatus according to the error diffusing method. In FIG. 1, reference numeral 40 denotes a diffused error calculation unit; 41 a memory for storing errors to be distributed (divisionally supplied) to a next line; 44 an address generation unit for supplying a write address and a read address to the memory; 50 a signal line for inputting a multi-value image; 51 a signal line for outputting a converted binary image; 52 a signal line for reading out errors distributed from a preceding line from the memory; 53 a signal line for writing errors to be distributed to the next line into the memory; 61 a signal line for supplying the write address to the memory; and 62 a signal line for supplying the read address.
In this instance, fundamental processes of the error diffusing method will now be explained by using FIGS. 2, 3, and 4. According to the error diffusing method, the multi-value image is binarized by distributing errors of a target pixel to the peripheral pixels in accordance with a value of an error diffusing mask.
FIG. 2 is a diagram showing an example of the error diffusing mask. In the diagram, * denotes a target pixel, a numerical value denotes a value indicating errors of which number of times of a value obtained by shifting the value of the target pixel to the right by three bits (an arithmetic operation of 1/8 by a bit arithmetic operation) are distributed to the pixels around the target pixel, and R denotes that the remaining errors of the errors distributed according to the numerical value are distributed. Namely, R indicates that a weight corresponding to the numerical value in FIG. 2 is added to the errors and the weighted errors are distributed to each of the peripheral pixels.
FIG. 3 shows an example of a part of a circuit for performing the error diffusing process in accordance with the error diffusing mask shown in FIG. 2 and also shows an example of a diffused error calculation unit of the prior art shown in FIG. 1.
In FIG. 3, reference numeral 1 denotes an adder for adding errors to be distributed to the target pixel 2 a subtracter for obtaining negative errors which the target pixel has; 3 a selector for selecting positive and negative errors of the target pixel by the decided color of the target pixel; and 4 a comparator for deciding the color of the target pixel. An output of the comparator 4 becomes a selection signal of the selector and also becomes a binary output. Reference numeral 5 denotes a shifter for shifting the value of the target pixel to the right by three bits (an arithmetic operation of 1/8 by a bit arithmetic operation); 6 a shifter for obtaining the remainder which occurs when the errors of the target pixel are distributed to the peripheral pixels; 7 a shifter for shifting the value which was shifted to the right by three bits to the left by one bit (an arithmetic operation of two times by the bit arithmetic operation); 9 an adder for adding the value shifted to the right by three bits and the memory read data designated by reference numeral 52 as errors distributed from the preceding line; 10 a delay circuit for delaying an output of the adder by the time corresponding to one clock; 8 an adder for adding the value shifted to the left by one bit and an output of the delay circuit; 11 a delay circuit for delaying an output of the adder by the time of one clock; 12 a delay circuit for delaying the value shifted to the right by three bits by the time of one clock; 14 an adder for adding the value shifted to the right by three bits and an output of the delay circuit; 13 a shifter for shifting the value shifted to the right by three bits to the left by one bit (the arithmetic operation of two times by the bit arithmetic operation); 15 an adder for adding an output of the adder and an output of the shifter; 16 a delay circuit for delaying an output of the adder by the time of one clock; 18 an adder for adding an output of the delay circuit and the value shifted to the right by three bits; 19 a delay circuit for delaying an output of the adder by the time of one clock; and 17 an adder for adding an output of the shifter to obtain the foregoing remainder and an output of the delay circuit. An output of the adder 17 corresponds to errors to be distributed to the next line and also becomes data to be written into the memory.
FIG. 4 is a timing chart for a step of calculating binary outputs according to the error diffusing method. In FIG. 4, CLK at the top stage denotes a clock signal (not shown) which is supplied to the one-clock delay circuit in FIG. 3 and the circuit shown in FIG. 3 operates synchronously with the clock. Reference numeral 60 in FIG. 4 denotes a value (hereinbelow, this value is called a unit error) of the signal line 60 and corresponds to the value shifted to the right by three bits of the errors of the target pixel and E.sub.N in the diagram denotes a unit error of the N-th pixel. Reference numeral 58 in FIG. 4 denotes a value of a signal line 58 in FIG. 3 and 3E.sub.N+2 +E.sub.N+1 in the diagram indicates a value obtained by adding the error which is three times as large as the unit error that of the (N+2)th pixel and the unit error of the (N+1)th pixel. Reference numeral 59 in FIG. 4 denotes a value of a signal line 59 and E.sub.N+2 +3E.sub.N+1 +E.sub.N in the diagram indicates a value obtained by adding the unit error of the (N+2)th pixel, the value which is three times as large as the unit error of the (N+1)th pixel, and the unit error of the N-th pixel. Reference numeral 53 in FIG. 4 denotes a value of the signal line 53 in FIG. 3 and R.sub.N+2 +E.sub.N+1 +3E.sub.N+E.sub.N-1 in the diagram indicates a value obtained by adding the remaining errors of the errors distributed to the peripheral pixels from the (N+2)th pixel, the unit error of the (N+1)th pixel, the value which is three times as large as the unit error of the N-th pixel, and the unit error of the (N-1)th pixel. Such a value corresponds to an error to be added to the N-th pixel of the next line and, consequently, is written into the memory. Reference numeral 61 in FIG. 4 denotes a value of the write address signal line 61 in FIG. 1 and indicates that the data to be written into the memory corresponds to data for which number of pixel. Reference numeral 52 in FIG. 4 denotes a value of the signal line 52 in FIG. 3 and M.sub.N in the diagram indicates the read data for the N-th pixel. Reference numeral 56 in FIG. 4 denotes a value of a signal line 56 in FIG. 3 and M.sub.N-1 +E.sub.N-3 in the diagram indicates a value obtained by adding the read data for the (N-1)th pixel and the unit error of the (N-3)th pixel. Reference numeral 57 in FIG. 4 denotes a value of a signal line 57 in FIG. 3 and M.sub.N-2 +E.sub.N-4 +2E.sub.N-3 in the diagram indicates a value obtained by adding the read data for the (N-2)th pixel, the unit error of the (N-4)th pixel, and a value which is two times as large as the unit error of the (N-3)th pixel.
Reference numeral 62 in FIG. 4 denotes a value of the read address signal line 62 in FIG. 1 and indicates that the data to be read out from the memory corresponds to data for which number of data.
In this manner, when the multi-value image is binarized by the error diffusing method, in order to calculate an error for each pixel, the writing and reading operations have to be executed for the memory in all processing cycles.
Consequently, in the prior art, as a memory device to store error data, a memory device having a plurality of input/output ports of a low integration degree, namely, a memory device in which an occupied area of a memory cell for storing data of one bit on one chip is large and an occupied area of a processing circuit is also large has to be used. Thus, a circuit scale is increased and it is difficult to realize an integration, namely, a miniaturization of an IC chip.